Embedded SRAM power record claimed
The firm used its in-house 65nm silicon-on-thin buried oxide (BOX) – SOTB – process for the prototype, and used substrate biasing to adjust the leakage/speed compromise.
This gets over challenges with conventional CMOS, such as the increased leakage with low-threshold transistors and high variability in gate threshold voltage.
“These problems result in increased power consumption in the stand-by mode and increased operating power due to the inability to lower operating voltages, which makes low power consumption difficult to achieve,” said Renesas.
A major source of threshold variation in conventional small transistors is that there are so few dopant atoms in the channel that a handful either way changes the threshold. With STOB, and other fully-depleted silicon-on-insulator (FDSoI) processes, there are no dopant atoms in the transistor channel to vary in number.
“This reduction in variations has a similar effect to the FinFET structure adopted in state-of-the-art SoCs,” said Renesas. “Reduction of the variations in transistor performance achieves stable operation at low voltages around 0.5V.”
Furthermore, substrate-biasing under a thin BOX layer allows significant changes in transistor threshold characteristics.
“Taking advantage of this feature, Renesas provides an on-chip regulator that can dynamically control the embedded SRAM substrate which enables one of four modes – normal, low-power, high-speed or stand-by – to be selected.
Normal to high-speed mode (zero substrate bias to forward bias) changes read access time 2.5x – from 4.58 to 1.84ns.
Reverse-bais in stand-by mode cuts leakage 1,000x compared with normal mode – to the 13.7nW/Mbit figure.
On top of this, Renesas has tackled active power consumption by fine-grained word line pulse width control – achieving up to 20% read power savings.
“Even if the variations in the characteristics of the embedded SRAM are reduced when adopting the SOTB structure, those variations cannot be reduced to zero,” said the firm. “Therefore it becomes significant to secure design margins such that the memory cell with the largest variation can operate.”
For cases where multiple SRAM macros are placed around the chip – in IoT ASSPs, for example – the required design margin in each SRAM macro unit will vary according to the probability with which the memory cell with the largest variations is included in the macro.
Conventionally, according to Renesas, the same worst case condition design margins were assigned to each macro so that reliable operation under worst case conditions could be guaranteed for all the macros on the chip – which meant that there were always macros for which the margins were excessive.
“To improve this situation, Renesas proposed a replica circuit method in which the read pulse width could be optimized in a fine-grained manner to target removal of those excessive design margins,” said the firm, leading to up to 20% read power savings.
The work was presented at the VLSI Symposia in Kyoto today.
Renesas expects to use the technology as an alternative to non-volatile memory for energy-harvesting and battery-powered applications in IoT, home electronics, and healthcare.
“The most commonly used procedure to reduce power consumption in stand-by mode is to cut off power to the circuit after saving any necessary data either to an external device or to internal non-volatile memory,” it said. “Although this method is effective when wait times are relatively long, in systems that frequently iterate the switching between the active and stand-by mode, the saving of data to non-volatile memory and the restart operation becomes a significant overhead. There are even cases where, inversely, this actually increases power consumption.”
Previous prototype embedded SRAM work at Renesas includes 28nm high-k metal gate (HKMG) structures, and high-performance 16nm finFET structures, which were later used in its R-Car automotive infotainment SoCs.